View CY62147EV18_4245394.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62147EV18 MoBL2TM
4-Mbit (256K x 16) Static RAM
Features

Very high speed: 55 ns Wide voltage range: 1.65V-2.25V Pin compatible with CY62147DV18 Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A Ultra low active power Typical active current: 2 mA @ f = 1 MHz Ultra low standby power Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in a Pb-free 48-Ball VFBGA package
consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) When a write operation is active (CE LOW and WE LOW).

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Functional Description
The CY62147EV18 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER POWER DOWN CIRCUIT
CE BHE WE CE OE BLE
A11
A12
A13
A15
BLE
Cypress Semiconductor Corporation Document #: 38-05441 Rev. *F
*
198 Champion Court
A16
*
A17
A14
BHE
San Jose, CA 95134-1709 * 408-943-2600 Revised August 01, 2007
CY62147EV18 MoBL2TM
Product Portfolio
Power Dissipation Product VCC Range (V) Min CY62147EV18LL 1.65 Typ [1] 1.8 Max 2.25 55 Speed (ns) Typ [1] 2 Operating ICC (mA) f = 1MHz Max 2.5 f = fmax Typ [1] 15 Max 20 Standby ISB2 (A) Typ [1] 1 Max 7
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3] Top View
1 BLE IO8 IO9 VSS VCC IO14 IO15 NC 2 OE BHE IO10 IO11 IO12 IO13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO1 IO3 IO4 IO5 WE A11 6 NC IO0 IO2 VCC VSS IO6 IO7 NC A B C D E F G H
Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 2. NC pins are not connected on the die. 3. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
Document #: 38-05441 Rev. *F
Page 2 of 12
CY62147EV18 MoBL2TM
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied .......................................... -55C to + 125C Supply Voltage to Ground Potential ........................... -0.2V to + 2.45V (VCCmax + 0.2V) DC Voltage Applied to Outputs in High Z State[4, 5] ............... -0.2V to 2.45V (VCCmax + 0.2V) DC Input Voltage[4, 5] ........... -0.2V to 2.45V (VCCmax + 0.2V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA
Operating Range
Device Range Ambient Temperature VCC[6] CY62147EV18LL Industrial -40C to +85C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current IOH = -0.1 mA IOL = 0.1 mA VCC =1.65V to 2.25V VCC =1.65V to 2.25V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC VCC(max)=2.25V IOUT = 0 mA CMOS levels VCC(max)=2.25V 1.4 -0.2 -1 -1 15 Test Conditions 55 ns Min 1.4 0.2 VCC+ 0.2 0.4 +1 +1 20 Typ[1] Max Unit V V V V A A mA
f = 1 MHz ISB1
2 1
2.5 7
mA A
Automatic CE Power Down CE > VCC - 0.2V, VCC(max)=2.25V Current-CMOS Inputs VIN > VCC - 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE, WE, BHE, and BLE) Automatic CE Power Down CE > VCC - 0.2V, Current-CMOS Inputs VIN > VCC - 0.2V or VIN < 0.2V, f=0 VCC(max)=2.25V
ISB2[7]
1
7
A
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max)=VCC+0.5V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05441 Rev. *F
Page 3 of 12
CY62147EV18 MoBL2TM
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board VFBGA Package 75 10 Unit C/W C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
VCC OUTPUT
Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH 1.80V 13500 10800 6000 0.80 V Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR[7] tCDR[8] tR
[9]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC= 1.0V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V
Min 1.0
Typ[1] 0.5
Max 5
Unit V A ns ns
0 tRC
Data Retention Waveform
Figure 3. Data Retention Waveform[10]
DATA RETENTION MODE VCC CE or BHE.BLE
Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
VCC(min)
tCDR
VDR > 1.0V
VCC(min)
tR
Document #: 38-05441 Rev. *F
Page 4 of 12
CY62147EV18 MoBL2TM
Switching Characteristics
Over the Operating Range [11, 12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[15] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High WE HIGH to Low Z[13, 14] Z[13] 10 45 35 35 0 0 35 35 25 0 18 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[13]
[13, 14]
Description
55 ns Min 55 55 10 55 25 5 18 10 18 0 55 55 10 18 Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE HIGH to High
Z[13] Z[13, 14]
CE LOW to Power Up CE HIGH to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[13] Z[13, 14] BLE/BHE HIGH to High
Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4 section. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05441 Rev. *F
Page 5 of 12
CY62147EV18 MoBL2TM
Switching Waveforms
Figure 4 shows the Read Cycle No.1 that is address transition controlled. [16, 17] Figure 4. Read Cycle No. 1
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5 shows the Read Cycle No.2 that is OE controlled. [17, 18] Figure 5. Read Cycle No. 2
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes: 16. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05441 Rev. *F
Page 6 of 12
CY62147EV18 MoBL2TM
Switching Waveforms (continued)
Figure 6 shows the Write Cycle No.1 that is WE Controlled. [15, 19, 20] Figure 6. Write Cycle No. 1
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA IO NOTE 21 tHZOE
tSD DATAIN
tHD
Figure 7 shows the Write Cycle No.2 that is CE Controlled. [15, 19, 20] Figure 7. Write Cycle No. 2
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 21 tHZOE
Notes: 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals.
tHD
DATAIN
Document #: 38-05441 Rev. *F
Page 7 of 12
CY62147EV18 MoBL2TM
Switching Waveforms (continued)
Figure 8 shows the Write Cycle No. 3 that is WE Controlled and OE LOW. [20] Figure 8. Write Cycle No. 3
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA IO NOTE 21 tHZWE DATAIN
tHD
tLZWE
Figure 9 shows Write Cycle No. 4 that is BHE/BLE Controlled and OE LOW. [20] Figure 9. Write Cycle No. 4
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 21
Document #: 38-05441 Rev. *F
Page 8 of 12
CY62147EV18 MoBL2TM
Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE BLE X H L H L L H L L H L X H L L H L L H L L H Inputs or Outputs High Z High Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High-Z Data Out (IO8-IO15); IO0-IO7 in High-Z High Z High Z High Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High-Z Data In (IO8-IO15); IO0-IO7 in High-Z Mode Deselect or Power Down Deselect or Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62147EV18LL-55BVXI Package Diagram Package Type Operating Range Industrial 51-85150 48-Ball VFBGA (Pb-free)
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05441 Rev. *F
Page 9 of 12
CY62147EV18 MoBL2TM
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm), 51- 85150
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
TOP VIEW
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
Document #: 38-05441 Rev. *F
Page 10 of 12
CY62147EV18 MoBL2TM
Document History Page
Document Title: CY62147EV18 MoBL2TM 4-Mbit (256K x 16) Static RAM Document Number: 38-05441 REV. ** *A ECN NO. 201580 247009 Issue Date 01/08/04 See ECN Orig. of Change AJU SYT New Datasheet Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCCMax from 2.20 to 2.25 V Changed VCC stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #15 (tLZBE) from Previous Revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35 ns Speed Bin Removed "L" version of CY62147EV18 Changed ball E3 from DNU to NC Changed ICC(typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC(max) value from 2 mA to 2.5 mA at f = 1 MHz Changed ICC(typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A Extended undershoot limit to -2V in footnote #5 Changed ICCDR Max from 2.5 A to 3 A Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced Package Name Column with Package Diagram Replaced 45ns speed bin with 55 ns Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters Changed tWC specification from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE specification from 18 ns to 20 ns Description of Change
*B
414820
See ECN
ZSD
*C *D
571786 908120
See ECN See ECN
VKN VKN
Document #: 38-05441 Rev. *F
Page 11 of 12
CY62147EV18 MoBL2TM
Document Title: CY62147EV18 MoBL2TM 4-Mbit (256K x 16) Static RAM Document Number: 38-05441 REV. *E *F ECN NO. Issue Date Orig. of Change VKN Description of Change Changed ICCDR specification from 3 A to 5 A
1045701 See ECN
1274728 See ECN VKN/AESA Changed tWC specification from 55 ns to 45 ns Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns Changed tHZWE specification from 20 ns to 18 ns
(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05441 Rev. *F
Revised August 01, 2007
Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

▲Up To Search▲

Price & Availability of CY62147EV18

	To Download CY62147EV18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .